1. Field of the Invention
The present invention relates to a high voltage switch circuit of a semiconductor device, and more particularly to, a high voltage switch circuit which can reduce a discharge time.
2. Discussion of Related Art
A NAND flash memory device requires a pumping voltage higher than an input power voltage in the program, erase and read operations. In the program operation, programming and verification operations are performed in a pair. A very lower bias is supplied to a word line in the verification operation than in the programming operation. This procedure is repeated until the verification operation is successfully performed within a maximum loop set in the two operations. A bias discharge time for the verification operation is quite long and more increased in the erase operation.
FIG. 1 is a waveform diagram showing discharge problems of a conventional high voltage switch circuit.
Referring to FIG. 1, a high voltage which is an output from a pumping unit is supplied according to a predetermined enable signal. When the high voltage is not supplied due to variations of the enable signal, a discharge time over about 1 μs is generated in the conventional high voltage switch circuit. That is, a general discharge circuit discharges a high voltage by using a high voltage NMOS transistor having its drain terminal connected to a charge pump terminal, its source terminal connected to a ground power, and its gate terminal connected to receive a power voltage. When only the power voltage is used, the discharge time is much more delayed in a low power voltage of the operation power voltage range than in a general mode. An NMOS size can be controlled to overcome the foregoing problems, which does not efficiently reduce the discharge time.